This application relies for priority upon Korean Patent Application No. 1999-42356, filed on Oct. 1, 1999, the contents of which arc herein incorporated by reference in their entirety.
The present invention relates to semiconductor memory devices and, more particularly, to a sense amplifier circuit, which is used in a nonvolatile semiconductor memory device.
An EPROM or EEPROM cell (or flash memory cell) typically is made from a floating-gate field effect transistor. The floating-gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a predetermined voltage is applied to the control gate. The nonconductive state is read by a sense amplifier as a xe2x80x9czeroxe2x80x9d bit (or as a xe2x80x9conexe2x80x9d bit). At this time, the programmed memory cell has an off state. The floating-gate conductor of a non-programed cell is neutrally charged (or slightly positively or negatively charged) such that the source-drain path under the non-programmed floating gate is conductive when the predetermined voltage is applied to the control gate. The conductive state is read by a sense amplifier as a xe2x80x9conexe2x80x9d bit (or as the xe2x80x9czeroxe2x80x9d bit). At this time, the non-programmed cell has an on state.
An array of a nonvolatile semiconductor memory device may contain millions of floating-gate memory cells arranged in rows and columns. The sources of each cell in a column are connected to a source-column line. The source-column line for a selected cell may be connected to reference potential or ground during reading of the selected cell by a sense amplifier. The drains of each cell in a column are connected to a separate bit line (drain-column line) and the drain-column line for a selected cell is connected to an input terminal of the sense amplifier during reading of the selected cell. The control gates of each cell in a row arc connected to a word line, and the word line for a selected cell is connected to the predetermined select voltage during reading of the selected cell.
During the read operation, the current through the selected cell is compared with a reference current to determine whether or not the selected cell is programmed with a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d. The reference current is derived from reference circuitry, which may include one or more floating-gate cells identical to the cell being read or may include a column of such reference s cells. The reference circuitry is connected to tie other input terminal of a current mirror type differential amplifier via a reference line. In order to determine whether a logic state of the selected memory cell is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the differential amplifier compares the voltage on the reference line with the voltage on the data line connected to the selected memory cell that is being road.
A conventional sense amplifier circuit with the above-described function is illustrated in FIG. 1.
Referring to FIG. 1, a reference number 12 indicates a floating-gate memory cell transistor, and reference numbers 14 and 16 indicate floating-gate reference cell transistors, respectively. A threshold voltage Vth of each of the serially-connected reference cell transistors 14 and 16 is identical to that of the memory cell with the transistor in its programmed state. This is also referred to as the memory cell transistor of the on state, or the xe2x80x9can on-cell transistorxe2x80x9d; or the programmed memory cell. A drain of the memory cell transistor 12 is supplied with a power supply voltage Vcc through a load transistor 20 connected in series with an NMOS transistor 18, whose gate is connected to a bias voltage Vbias. Similarly, a drain of the reference cell transistor 16 is supplied with the power supply voltage Vcc through a load transistor 24 connected in series with an NMOS transistor 22, the gate of which is coupled to a bias voltage VRBias. A sense node Vs between the transistors 18 and 20 and a reference node VR between the transistors 22 and 24 arc connected to corresponding input terminals of a differential amplifier circuit 26, respectively.
A graph showing current characteristic curves of die on cell, the off cell and the reference cell is illustrated in FIG. 2. In FIG. 2, the curve Ion represents a current flowing via the un-programmed memory cell (referred to as xe2x80x9con-cell currentxe2x80x9d), the curve off represents a current flowing via the programmed memory cell (referred to as xe2x80x9coff-cell currentxe2x80x9d), and the curve Iref represents a current flowing via the reference cell (referred to as xe2x80x9creference-cell currentxe2x80x9d). As described in FIG. 1, since the reference cell is composed of two on-cell transistors serially connected to each other, the reference-cell current Iref is half the on-cell current Ion.
In the conventional sense amplifier circuit, as illustrated in FIG. 2, the reference-cell current Iref is varied as a gate voltage Vg applied to the gates of the transistors 14 and 16 is varied. Herein, as well known to ones skilled in the art, since the gate voltage Vg is generated by use of the power supply voltage Vcc as a power source, it may be varied according to the variation of the power supply voltage Vcc. In this case, as illustrated in FIG. 2, the minimum operating voltage of the conventional sense amplifier circuit 10 is limited by the threshold voltage Vth1 of the on-cell transistor, while the maximum operating voltage thereof is limited by a gate voltage Vcmax at a point where the off-cell current Off curve intersects the reference-cell current Iref curve.
In the conventional sense amplifier circuit, a problem arises when the gate voltage Vg is increased above the maximum operating voltage Vccmax. That is, it is impossible to sense a logic state of the off cell. It means that a range of the operating voltage of the conventional sense amplifier circuit 10 is limited by the variation of the power supply voltage (or the gate voltage of the memory/reference cell transistor). That is, the operating voltage range of the circuit 10 is narrow, and thus not easily usable.
It is therefore an object of the invention to provide a sense amplifier circuit of a nonvolatile semiconductor memory device which generates a reference-cell current existing between an on-cell current and an off-cell current.
It is another object of the invention to provide a sense amplifier circuit of a nonvolatile semiconductor memory device which is capable of preventing an operating voltage range from being limited according to a variation of a power supply voltage (or gate voltage variation of a memory/reference cell).
In accordance with this and other objects, advantages and features of the present invention, a sense amplifier circuit for a semiconductor memory device is provided which a memory cell and a reference cell. The memory cell has either a first threshold voltage or a second threshold voltage, and a reference cell has a third threshold voltage between the first threshold voltage and the second threshold voltage, regardless of the value of Vg.
In the sense amplifier circuit, a first and a second load transistors is further provided in the sense amplifier. The first load transistor is coupled between a power supply voltage and a data line connected to the memory cell, and a second load transistor is coupled between the power supply voltage and a reference line connected to the reference cell. Furthermore, the sense amplifier circuit includes a resistor coupled in parallel to the reference cell and a differential amplifier. The differential amplifier receives signals from the data line and from the reference line commonly coupled to the reference cell and the resistor, and outputs either a high level or a low level to a logic state of the memory cell based on the potential of the reference line.